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BU4219 Scheda tecnica(PDF) 8 Page - Rohm

Il numero della parte BU4219
Spiegazioni elettronici  Low Voltage Free Delay Time Setting CMOS Voltage Detector IC Series
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Produttore elettronici  ROHM [Rohm]
Homepage  http://www.rohm.com
Logo ROHM - Rohm

BU4219 Scheda tecnica(HTML) 8 Page - Rohm

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Technical Note
8/11
BU42□□G series, BU42□□F series, BU42□□FVE series,
BU43□□G series, BU43□□F series, BU43□□FVE series
www.rohm.com
2009.11 - Rev.C
© 2009 ROHM Co., Ltd. All rights reserved.
Notes for use
1. Absolute maximum range
Absolute Maximum Ratings are those values beyond which the life of a device may be destroyed. We cannot be defined the
failure mode, such as short mode or open mode. Therefore a physical security countermeasure, like fuse, is to be given
when a specific mode to be beyond absolute maximum ratings is considered.
2 . GND potential
GND terminal should be a lowest voltage potential every state.
Please make sure all pins that are over ground even if include transient feature.
3 . Electrical Characteristics
Be sure to check the electrical characteristics, that are one the tentative specification will be changed by temperature,
supply voltage, and external circuit.
4 . Bypass Capacitor for Noise Rejection
Please put into the to reject noise between VDD pin and GND with 1uF over and between VOUT pin and GND with 1000pF.
If extremely big capacitor is used, transient response might be late. Please confirm sufficiently for the point.
5 . Short Circuit between Terminal and Soldering
Don’t short-circuit between Output pin and VDD pin, Output pin and GND pin, or VDD pin and GND pin. When soldering the
IC on circuit board please is unusually cautious about the orientation and the position of the IC. When the orientation is
mistaken the IC may be destroyed.
6 . Electromagnetic Field
Mal-function may happen when the device is used in the strong electromagnetic field.
7. The VDD line inpedance might cause oscillation because of the detection current.
8. A VDD -GND capacitor (as close connection as possible) should be used in high VDD line impedance condition.
9. Lower than the mininum input voltage makes the VOUT high impedance, and it must be VDD in pull up (VDD) condition.
10. Case of needless Delay time, recommended to insert more 470kΩ resister between VDD and CT.
Recommended value of RL Resistar is over 50kΩ (VDET=1.5~4.8V),over 100kΩ (VDET=0.9~1.4V).
12. This IC has extremely high impedance terminals. Small leak current due to the uncleanness of PCB surface might cause
unexpected operations. Application values in these conditions should be selected carefully. If 10MΩ leakage is assumed
between the CT terminal and the GND terminal, 1MΩ connection between the CT terminal and the VDD terminal would be
recommended. Also, if the leakage is assumed between the VOUT terminal and the GND terminal, the pull up resistor
should be less than 1/10 of the assumed leak resistance.
The value of RCT depends on the external resistor that is connected to CT terminal, so please consider the delay time
that is decided by τ × RCT × CCT changes.


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