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BU2152FS Scheda tecnica(PDF) 6 Page - Rohm |
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BU2152FS Scheda tecnica(HTML) 6 Page - Rohm |
6 / 25 page BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS Technical Note 6/24 www.rohm.com 2009.06 - Rev.A © 2009 ROHM Co., Ltd. All rights reserved. ● Operating description (1) Data clear When the reset terminal (CLR, CLB) is set to “L”, the content of all latch circuits are set to “H”, and all parallel outputs are initialised. (For model with reset terminal only) (2) Data transfer Serial data is sequentially input to the shift register during the rise of the clock time (strobe signal is not active). When the strobe signal is active, the content of the shift register are transferred to the latch circuit. (3) Cascade connection Serial input data is output from the serial output through the shift register, regardless of the strobe signal. (except for BU2050F, BU2092F/BU2092FV) ● Application circuit Fig. 1 ● Interfaces BU2050F BU2050F BU2092F/BU2092FV BU2092F/BU2092FV DATA, CLOCK, STB, CLR P1~P8 DATA, CLOCK, LCK, OE Q0~Q11 BU2099FV BU2099FV BU2099FV BU2152FS DATA, CLOCK, LCK, OE Q0~Q11 SO CLOCK, DATA, STB, CLB BU2152FS BU2152FS P1~P28 SO VDD Serial data input Clock input Strobe input Latch input P1 P2 Pn-2 Pn-1 Pn Serial data output VSS P1 P2 Pn-2 Pn-1 Pn VSS VDD VSS MPU C1 (*) (*C1 must be placed as close to the terminal as possible.) VDD Serial data input Clock input Strobe input Latch input Serial data output INPUT GND(VSS) GND(VSS) VDD GND(VSS) VDD OUTPUT GND(VSS) IN GND(VSS) GND(VSS) VDD VDD OUT GND(VSS) GND(VSS) VDD OUT OUT GND(VSS) VSS VDD VDD VSS VSS GND(VSS) VDD VDD VDD GND(VSS) GND(VSS) GND(VSS) VDD VDD GND(VSS) VDD GND(VSS) GND(VSS) VDD GND(VSS) VDD GND(VSS) VDD IN (only OE pin) |
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