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TDA9950 Scheda tecnica(PDF) 7 Page - NXP Semiconductors

Il numero della parte TDA9950
Spiegazioni elettronici  CEC/I2C-bus translator
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

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TDA9950_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2009
7 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
Table 10.
CCR - TDA9950 Control Register (address 03h) bit description (Read/Write)
Bit
Symbol
Description
7
RESET
RESET: Resets the TDA9950. Any transmission in progress
will be completed first - the reset occurs once the TDA9950
returns to the idle state. All default values will be restored.
0 = no specific action.
1 = resets the TDA9950.
6
ON_OFF
ON_OFF:
0 = the TDA9950 is disabled (after completion of any pending
CEC transmission or reception) and will no longer
acknowledge any message on the CEC line or accept any
message for transmission.
1 = the TDA9950 is enabled and will acknowledge messages
according to the logical address bits in the CEC Address ACK
High and CEC Address ACK Low registers.
5 to 0
-
not used
Table 11.
ACKH - CEC Address ACK High register (address 04h) bit description
(Read/Write)
Bit
Symbol
Description
7
reserved
reserved (must be set to 0)
6 to 0
ACKH[6:0]
CEC Address ACK High register
For each bit:
0 = messages to the corresponding logical address will not be
acknowledged.
1 = messages to the corresponding logical address are
acknowledged and forwarded to the host.
Table 12.
ACKL - CEC Address ACK Low register (address 05h) bit description
(Read/Write)
Bit
Symbol
Description
7 to 0
ACKL[7:0]
CEC Address ACK Low register
For each bit:
0 = messages to the corresponding logical address will not be
acknowledged.
1 = messages to the corresponding logical address are
acknowledged and forwarded to the host.
Table 13.
CCONR - CEC Configuration Register (address 06h) bit description (Read/Write)
Bit
Symbol
Description
7 to 5
-
not used


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