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TDA9950 Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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TDA9950 Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
3 / 22 page TDA9950_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 22 October 2009 3 of 22 NXP Semiconductors TDA9950 CEC/I2C-bus translator 6. Block diagram 7. Pinning information 7.1 Pinning 7.2 Pin description Fig 1. Block diagram 001aag922 TDA9950 CPU DATA RAM internal bus CEC-BUS CEC_IN CEC_OUT XTAL1 XTAL2 A0 A1 SCL SDA INT INT_POL RST CONFIGURABLE OSCILLATOR CRYSTAL POWER-ON RESET INTERRUPT I2C-BUS Fig 2. Pin configuration TDA9950 RSVD1 A0 INT A1 CEC_OUT INT_POL RST RSVD7 VSS RSVD6 XTAL1 VDD XTAL2 RSVD5 CEC_IN RSVD4 SDA RSVD3 SCL RSVD2 001aag923 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 Table 3. Pin description Symbol Pin Type[1] Description RSVD1 1 I RSVD1 — Reserved pin; shall be connected to ground INT 2 O INT — Interrupt line to the host processor to indicate data is available for reading. The polarity of this signal depends on the state of pin INT_POL. CEC_OUT 3 O CEC_OUT — Output for CEC line (open-drain). |
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