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74ABT821 Scheda tecnica(PDF) 4 Page - NXP Semiconductors |
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74ABT821 Scheda tecnica(HTML) 4 Page - NXP Semiconductors |
4 / 16 page 74ABT821_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 25 February 2010 4 of 16 NXP Semiconductors 74ABT821 10-bit D-type flip-flop; positive-edge trigger; 3-state 6. Functional description 6.1 Function table [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition. Table 3. Function table[1] Input Internal register Output Operating mode OE CP D0 to D9 Q0 to Q9 L ↑ l L L load and read register L ↑ hH H L NC X NC NC hold H NC X NC Z disable outputs H ↑ Dn Dn Z |
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