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AD5174 Scheda tecnica(PDF) 7 Page - Analog Devices

Il numero della parte AD5174
Spiegazioni elettronici  Single-Channel, 1024-Position, Digital Rheostat with SPI Interface and 50-TP Memory
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5174 Scheda tecnica(HTML) 7 Page - Analog Devices

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AD5174
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC
VDD 1
2
A
10
9 SCLK
VSS
3
W
4
SDO
8
7
5
EXT_CAP
DIN
6 GND
*LEAVE FLOATING OR CONNECTED TO VSS.
AD5174
VDD 11
VSS
22
A
33
W
44
SDO
10
9
8
SCLK
7
5
EXT_CAP
DIN
6
GND
AD5174
TOP VIEW
(Not to Scale)
SYNC
(EXPOSED
PAD)*
Figure 5. MSOP Pin Configuration
Figure 6. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
2
A
Terminal A of RDAC. VSS ≤ VA ≤ VDD.
3
W
Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
4
VSS
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors
and 10 μF capacitors.
5
EXT_CAP
External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage
rating of ≥7 V.
6
GND
Ground Pin, Logic Ground Reference.
7
SDO
Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data
from the shift register in daisy-chain mode or in readback mode.
8
DIN
Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit
input register.
9
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be
transferred at rates of up to 50 MHz.
10
SYNC
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks.
The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken
high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored
by the RDAC.
EPAD
Exposed Pad
Leave floating or connected to VSS


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