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ST8016 Scheda tecnica(PDF) 7 Page - Sitronix Technology Co., Ltd.

Il numero della parte ST8016
Spiegazioni elettronici  160 Output LCD Common/ Segment Driver IC
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Produttore elettronici  SITRONIX [Sitronix Technology Co., Ltd.]
Homepage  http://www.sitronix.com.tw
Logo SITRONIX - Sitronix Technology Co., Ltd.

ST8016 Scheda tecnica(HTML) 7 Page - Sitronix Technology Co., Ltd.

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ST8016
Ver 2.0
Page 7/28
2008/05/07
8
FUNCTIONAL DESCRIPTION
8.1
Pin Functions
(Segment mode)
SYMBOL
FUNCTION
VDD
Logic system power supply pin, connected to +2.5 to +5.5 V.
VSS
Ground pin, connected to 0 V.
V0L, V0R
V12L, V12R
V43L, V43R
Bias power supply pins for LCD drive voltage
Ÿ
Normally use the bias voltages set by a resistor divider
Ÿ
Ensure that voltages are set such that VSS < V43 < V12 < V0.
Ÿ
ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular
voltage which is assigned by specification for each power pin
DI7-DI0
Input pins for display data
Ÿ
In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0.
Connect DI7-DI4 to VSS or VDD.
Ÿ
In 8-bit parallel input mode, input data into the 8 pins, DI7-Dl0.
Ÿ
Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT
PINS" in Functional Operations.
XCK
Clock input pin for taking display data
* Data is read at the falling edge of the clock pulse.
LP
Latch pulse input pin for display data
Ÿ
Data is latched at the falling edge of the clock pulse.
L/R
Input pin for selecting the reading direction of display data
Ÿ
When set to VSS level "L", data is read sequentially from Y160 to Y1.
Ÿ
When set to VDD level "H", data is read sequentially from Y1 to Y160.
Ÿ
Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT
PINS" in Functional Operations.
/DISPOFF
Control input pin for output of non-select level
Ÿ
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Ÿ
When set to VSS level "L", the LCD drive output pins (Y1-Y160) are set to level Vss.
Ÿ
When set to "L", the contents of the line latch are reset, but the display data are read in the
data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is
canceled,
the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at
the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond
to what is shown in AC characteristics, it cannot output the reading data correctly.
Ÿ
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
FR
AC signal input pin for LCD drive waveform
Ÿ
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Ÿ
Normally it inputs a frame inversion signal.
Ÿ
The LCD drive output pins' output voltage levels can be set using the line latch output signal
and the FR signal.
Ÿ
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
MD
Mode selection pin
Ÿ
When set to VSS level "L", 4-bit parallel input mode is set.
Ÿ
When set to VDD level "H", 8-bit parallel input mode is set.
Ÿ
Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT
PINS" in Functional Operations.
S/C
Segment mode/common mode selection pin
Ÿ
When set to VDD level "H", segment mode is set.
ElO1, EIO2
Input/output pins for chip selection
Ÿ
When L/R input is at VSS level "L", ElO1 is set for output, and EIO2 is set for input.
Ÿ
When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output.
Ÿ
During output, set to "H" while LP • XCK is "H" and after 160 bits of data have been read, set


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