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ST7585 Scheda tecnica(PDF) 11 Page - Sitronix Technology Co., Ltd. |
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ST7585 Scheda tecnica(HTML) 11 Page - Sitronix Technology Co., Ltd. |
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11 / 51 page  ST7585 Ver 1.0c 11/51 2009/04/14 7. FUNCTIONS DESCRIPTION Microprocessor Interface Chip Select Input CSB pin is used for chip selection. ST7585 can interface with an MPU when CSB is "L". When CSB is “H”, the inputs of A0, ERD and RWR with any combination will be ignored and D[7:0] are high impedance. In 3-Line and 4-Line serial interface, the internal shift register and serial counter are reset when CSB is “H”. Parallel / Serial Interface ST7585 has types of interface for kinds of MPU. The MPU interface is selected by PS[2:0] pins as shown in table 1. Table 1. Parallel/Serial Interface Mode PS2 PS1 PS0 CSB A0 ERD RWR D[7:0] MPU Interface “L” “L” “L” 3-Line SPI interface “L” “L” “H” --- --- --- --- Refer to serial interface. 4-Line SPI interface “L” “H” “L” E R/W 6800-series parallel interface “L” “H” “H” CSB A0 /RD /WR D[7:0] 8080-series parallel interface “H” “L” “L” --- --- --- --- Refer to serial interface. I 2C Interface * The un-used pins are marked as “---” and should be fixed to “H” by VDD1. Parallel Interface The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS0 (fix PS2=L, PS1=H) as shown in table 2. The data transfer type is determined by signals of A0, ERD and RWR as shown in table 3. Table 2. Microprocessor Selection for Parallel Interface PS2 PS1 PS0 CSB A0 ERD RWR D[7:0] MPU Interface “L” “H” “L” E R/W 6800-series “L” “H” “H” CSB A0 /RD /WR D[7:0] 8080-series Table 3. Parallel Data Transfer Common 6800-series 8080-series A0 E (ERD) R/W (RWR) /RD (ERD) /WR (RWR) Description “H” “H” “H” “L” “H” Display data read out “H” “H” “L” “H” “L” Display data write “L” “H” “H” “L” “H” Internal status read “L” “H” “L” “H” “L” Writes to internal register (instruction) NOTE: In 6800-series interface mode, fixing E (ERD) pin at high can use CSB as enable signal instead. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0 and R/W (RWR) pins as defined in 6800-series mode. Setting Serial Interface Interface PS[2:0] CSB, A0, ERD, RWR D[7:0] 3-Line SPI “L, L, L” SCLK, SDA, ---, CSB, ---, ---, ---, --- 4-Line SPI “L, L, H” SCLK, SDA, A0, CSB, ---, ---, ---, --- I 2C “H, L, L” --- SCLK, SDA_IN, SDA_OUT, SDA_OUT, SDA_OUT, ---, SA1, SA0 * The un-used pins are marked as “---” and should be fixed to “H” by VDD1. Note: 1. The option setting to be “H” should connect to VDD1. 2. The option setting to be “L” should connect to VSS1. |
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