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AD9393BBCZRL-80 Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD9393BBCZRL-80 Scheda tecnica(HTML) 8 Page - Analog Devices |
8 / 40 page AD9393 Rev. 0 | Page 8 of 40 DESIGN GUIDE GENERAL DESCRIPTION The AD9393 is a fully integrated solution for receiving DVI/ HDMI signals and is capable of decoding HDCP-encrypted signals through connections to an external EEPROM. The circuit is ideal for providing an interface for HDTV monitors or as the front end to high performance video scan converters. Implemented in a high performance CMOS process, the interface can capture signals with pixel rates of up to 80 MHz. The AD9393 includes all necessary circuitry for decoding TMDS signaling including those encrypted with HDCP. Included in the output formatting is a color space converter (CSC), which accommodates any input color space and can output any color space. All controls are programmable via a 2-wire serial interface. Full integration of these sensitive mixed signal functions makes system design straight forward and less sensitive to the physical and electrical environment. DIGITAL INPUTS The digital control inputs (I2C) on the AD9393 operate to 3.3 V CMOS levels. In addition, all digital inputs except the TMDS inputs (HDMI/DVI) are 5 V tolerant. Applying 5 V to them does not cause any damage. The TMDS input pairs (Rx0±, Rx1±, Rx2±, and RxC±) must maintain a 100 Ω differential impedance (through proper PCB layout) from the connector to the input where they are internally terminated (50 Ω to 3.3 V). If additional ESD protection is desired, using a low capacitance ESD protection varistor offers 8 kV of protection to the HDMI TMDS lines. SERIAL CONTROL PORT The serial control port is designed for 3.3 V logic. However, it is tolerant of 5 V logic signals. OUTPUT SIGNAL HANDLING The digital outputs operate from 1.8 V to 3.3 V (VDD). POWER MANAGEMENT To determine the correct power state, the AD9393 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down ball. There are three power modes: full power, auto power-down, and power-down. Table 5 summarizes how the AD9393 determines which power mode to use and which circuitry is powered on/off in each of these modes. The power-down command has first priority and the automatic circuitry second priority. The power-down ball (Ball B8—polarity set by Register 0x26[3]) can drive the chip into two power-down options. Bit 2 of Register 0x26 controls these two options. Bit 0 controls whether the chip is powered down or the outputs are placed in high impedance mode. Bit 7 to Bit 4 of Register 0x26 control whether the outputs, Sony/ Philips digital interface (S/PDIF), or Inter-IC Sound bus (I2S or IIS) outputs are in high impedance mode or not. See the 2-Wire Serial Control Register Detail section for the details. Table 5. Power-Down Mode Descriptions Mode Inputs Power-On/Comments Power-Down1 Auto PD Enable2 Full Power 1 X Everything Auto Power-Down 1 1 Serial bus, sync activity detect, band gap reference Power-Down 0 X Serial bus, sync activity detect, band gap reference 1 Power-down is controlled via Bit 0 in Register 0x26. 2 Auto power-down is controlled via Bit 7 in Register 0x27. |
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