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AZP54VG Scheda tecnica(PDF) 3 Page - Arizona Microtek, Inc |
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AZP54VG Scheda tecnica(HTML) 3 Page - Arizona Microtek, Inc |
3 / 9 page AZP51 AZP52 AZP53 AZP54 December 2009 * REV - 2 www.azmicrotek.com 3 SIGNAL DESCRIPTION PIN/PAD FUNCTION D Sine or LVCMOS Input Q,Q ¯ LVPECL Outputs EN Output Enable DIV_SEL Divide Select (AZP53 only) EN_SEL Enable Select (AZP53 only) VDD Positive Supply GND Negative Supply (Ground) DIV-SEL OPERATION PART NUMBER DIV-SEL DIVIDE RATIO AZP51 AZP54 -2 ÷1 AZP52 -2 ÷2 NC1,L ÷1 AZP53 H ÷2 1. NC – no connection 2. Internally connected FUNCTIONAL OPERATION INPUTS OUTPUTS PART NUMBER EN_SEL 7 EN D EN LOGIC EN PULLUP/ PULLDOWN Q Q ¯ L L8 H8 NC1, H H H8 L8 AZP51 AZP52 -2 L X5 Active High4 Pullup Z6 Z6 L L8 H8 NC1, L H H8 L8 NC1, H H X5 Active Low3 Pulldown Z6 Z6 L L8 H8 NC1, H H H8 L8 AZP53 L L X5 Active High4 Pullup Z6 Z6 L L H NC1, L H H L AZP54 -2 H X5 Active Low3 Pulldown Z6 Z6 1. NC – no connection 2. Internally tied 3. Active Low: Output enabled when EN low, Tri-state when EN high 4. Active High: Output enabled when EN high, Tri-state when EN low 5. X – Don’t care 6. Z – High impedance 7. EN_SEL input has an internal pullup resistor 8. ÷1 modes only |
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