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TC5565AFL-10 Scheda tecnica(PDF) 1 Page - Toshiba Semiconductor |
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TC5565AFL-10 Scheda tecnica(HTML) 1 Page - Toshiba Semiconductor |
1 / 9 page TOSHIBA MOS MEMORY PRODUCTS TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 DESCRIPTION The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and operates from a single 5V supply. Advanced circuit techniques provide both high speed and low power features with a maximum operating current of 5mA/MHz and maximum access time of 100ns/120ns/150ns. When CE2 is a logical low or \CEl is a logical high, the device is placed in low power standby mode in which standby current is 2uA typically. The TC5565APL/AFL has three control inputs. Two chip enable (\CE1, CE2) allow for device selection and data retention control, and an output enable input (\OE) provides fast memory access. Thus the TC5565APL/AFL is suitable for use in various microprocessor application systems where high speed, low power, and battery back up are required. The TC5565APL also features pin compatibility with the 64K bit EPROM (TMM2764D). RAM and EPROM are then interchangeable in the same socket, resulting in flexibility in the definition of the quantity of RAM versus EPROM in microprocessor application systems. The TC5565APL is offered in a dual-in-line 28 pin standard plastic package. The TC5565AFL is offered in 28 pin mini Flat Package. FEATURES • Low Power Dissipation 27.5mW/MHz(Max.) operating • Standby Current: 100uA(Max.) Ta=70°C • Access Time TC5565APL/AFL-10 : 100ns(Max.) TC5565APL/AFL-12 : 120ns(Max.) TC5565APL/AFL-15 : 150ns(Max.) • 5V Single Power Supply - • Power Down Features: CE2, \CE1 • Fully Static Operation Data Retention Supply Voltage: 2.0-5.5V • Directly TTL Compatible : All Inputs and Outputs • Pin Compatible with 2764 type EPROM • TC5565APL Family (Package Type) Package Type Device Name 600 mil DIP TC5565APL 300 mil DIP (Slim Package) *TC5563APL Flat Package (SOP) TC5565AFL * See TC5563APL Technical Data. PIN CONNECTION (TOP VIEW) AO-A12 Address Inputs R/W Read/Write Control Input \OE Output Enable Input \CE1, CE2 Chip Enable Inputs I/O1 – I/O8 Data Input/Output VDD Power (+5V) GND Ground N.C. No Connection BLOCK DIAGRAM |
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