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ATmega128 Scheda tecnica(PDF) 94 Page - ATMEL Corporation |
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ATmega128 Scheda tecnica(HTML) 94 Page - ATMEL Corporation |
94 / 386 page 94 2467S–AVR–07/09 ATmega128 tive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk T0). The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). See “Output Compare Unit” on page 95. for details. The compare match event will also set the compare flag (OCF0) which can be used to generate an output compare interrupt request. Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise form must be used (i.e., TCNT0 for accessing Timer/Counter0 counter value and so on). The definitions in Table 51 are also used extensively throughout the document. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clk T0 is by default equal to the MCU clock, clkI/O. When the AS0 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asyn- chronous Status Register – ASSR” on page 107. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 110. Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 35 shows a block diagram of the counter and its surrounding environment. Figure 35. Counter Unit Block Diagram Table 51. Definitions BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The assignment is dependent on the mode of operation. DATA BUS TCNTn Control Logic count TOVn (Int.Req.) top bottom direction clear TOSC1 T/C Oscillator TOSC2 Prescaler clk I/O clk Tn |
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