CS470xx Data Sheet

Audio SOC Processor Family

4

Copyright 2009 Cirrus Logic

DS787PP1

5.17.2 Analog Output Characteristics (Automotive) ........................................................................ 31

5.17.3 Combined DAC Interpolation & On-chip Analog Filter Response ........................................ 32

6. Ordering Information ............................................................................................................33

7. Environmental, Manufacturing, & Handling Information ..................................................33

8. Device Pinout Diagram .........................................................................................................34

8.1 CS47048, 100-Pin LQFP Pinout Diagram ........................................................................................... 34

8.2 CS47028, 100-Pin LQFP Pinout Diagram ........................................................................................... 35

8.3 CS47024, 100-Pin LQFP Pinout Diagram ........................................................................................... 36

9. 100-pin LQFP with Exposed Pad Package Drawing .........................................................36

10. Parameter Definitions .........................................................................................................38

10.1 Dynamic Range ................................................................................................................................. 38

10.2 Total Harmonic Distortion + Noise ..................................................................................................... 38

10.3 Frequency Response ........................................................................................................................ 38

10.4 Interchannel Isolation ........................................................................................................................ 38

10.5 Interchannel Gain Mismatch .............................................................................................................. 38

10.6 Gain Error .......................................................................................................................................... 38

10.7 Gain Drift ........................................................................................................................................... 38

11. Revision History ..................................................................................................................38

Figures

Figure 1. CS47048 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. CS47028 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. CS47024 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. RESET Timing at Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. RESET Timing after Power is Stable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 7. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Serial Control Port - SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. Serial Control Port - I2C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. Serial Control Port - I2C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 12. Digital Audio Output Port Timing, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 13. Digital Audio Output Port Timing, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14. ADC Single-Ended Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15. ADC Differential Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 16. DAC Single-Ended Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17. DAC Differential Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32