TSB41LV06

IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

1

POST OFFICE BOX 655303

1394–1995 Standard for High Performance

(Draft 2.0)

Debounce, Arbitrated Short Reset,

Multispeed concatenation, Arbitration

Acceleration, Fly-by Concatenation, Port

Disable/Suspend/Resume

Ports at 100/200/400 Megabits per Second

(Mbits/s)

Active Connection to Remote Node

in Battery Powered Applications include:

Automatic Device Power-Down during

Suspend, Device Power-Down Pin, Link

Interface Disable via LPS, and Inactive

Ports Powered Down

Arbitration Functions

Data-Strobe Bit Level Encoding

Clock

Low Cost TI

™ Bus-Holder Isolation and

Optional Annex J Electrical Isolation

Through 2/4/8 Parallel Lines at 49.152 MHz

Transmit, Receive Data at 100/200/400

Mbits/s, and Link-Layer Controller Clock at

49.152 MHz

Using 3.3-V and 5-V Supplies

(PHY) Using 3.3-V and 5-V Supplies

for System Power Management

Contender Bit, Power Class Bits, Link

Active Bit and P1394a Features

i.LINK

™ Implementation of IEEE Std 1394

(PZP) Thermally Enhanced Package

description

The TSB41LV06 provides the digital and analog transceiver functions needed to implement a six-port node in

a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The

transceivers include circuitry to monitor the line conditions as needed for determining connection status, for

initialization and arbitration, and for packet reception and transmission. The TSB41LV06 is designed to interface

with a Link Layer Controller (LLC), such as the TSB12LV22, TSB12LV21, TSB12LV31, TSB12LV41, or

TSB12LV01.

The TSB41LV06 requires only an external 24.576 MHz crystal as a reference. An external clock may be

provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates

the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock

signals used to control transmission of the outbound encoded Strobe and Data information. A 49.152 MHz clock

signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization

of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops

operation of the PLL.

Copyright

© 1999, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

†Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.

i.LINK is a trademark of Sony Corporation

FireWire is a trademark of Apple Computers Incorporated.