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TSB41LV02APAP Scheda tecnica(PDF) 7 Page - Texas Instruments

Il numero della parte TSB41LV02APAP
Spiegazioni elettronici  IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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TSB41LV02APAP Scheda tecnica(HTML) 7 Page - Texas Instruments

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TSB41LV02A
IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER
SLLS400A – JANUARY 2000 – REVISED MAY 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
TYPE
I/O
DESCRIPTION
NAME
NO.
TYPE
I/O
DESCRIPTION
AGND
32, 33,
39, 48,
49, 50
Supply
Analog circuit ground pins. These pins should be tied together to the low impedance circuit board
ground plane.
AVDD
30, 31,
42, 51,
52
Supply
Analog circuit power pins. A combination of high frequency decoupling capacitors near each pin is
suggested, such as paralleled 0.1
µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are
also recommended. These supply pins are separated from PLLVDD and DVDD internal to the device
to provide noise isolation. They should be tied at a low impedance point on the circuit board.
C/LKON
19
CMOS
I/O
Bus manager contender programming input and link-on output. On hardware reset, this pin is used
to set the default value of the contender status indicated during self-ID. Programming is done by
tying the pin through a 10-k
Ω resistor to a high (contender) or low (not contender). The resistor
allows the link-on output to override the input.
Following hardware reset, this pin is the link-on output, which is used to notify the LLC to power-up
and become active. The link-on output is a square-wave signal with a period of approximately 163 ns
(8 SYSCLK cycles) when active. The link-on output is otherwise driven low, except during Hardware
Reset when it is high impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit is cleared) and when:
• The PHY receives a link-on PHY packet addressed to this node,
• The PEI (port-event interrupt) register bit is 1, or
• Any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or
STOI (state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt
enable) register bit is also 1.
Once activated the link-on output will continue active until the LLC becomes active (both LPS active
and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the
link-on output would otherwise be active because one of the interrupt bits is set (i.e., the link-on
output is active due solely to the reception of a link-on PHY packet.
Note: If an interrupt condition exists which would otherwise cause the link-on output to be activated if
the LLC were inactive, the link-on output will be activated when the LLC subsequently becomes
inactive.
CNA
3
CMOS
O
Cable not active output. This pin is asserted high when there are no ports receiving incoming bias
voltage.
CPS
24
CMOS
I
Cable power status input. This pin is normally connected to cable power through a 400 k
Ω resistor.
This circuit drives an internal comparator that is used to detect the presence of cable power.
CTL0
CTL1
4
5
CMOS
5 V tol
I/O
Control I/Os. These bidirectional signals control communication between the TSB41LV02A and the
LLC. Bus holders are built into these terminals.
D0 – D7
6, 7, 8, 9,
10, 11,
12, 13
CMOS
5 V tol
I/O
Data I/Os. These are bidirectional data signals between the TSB41LV02A and the LLC. Bus holders
are built into these terminals.
DGND
17, 18,
63, 64
Supply
Digital circuit ground pins. These pins should be tied together to the low impedance circuit board
ground plane.
DVDD
25, 26
61, 62
Supply
Digital circuit power pins. A combination of high frequency decoupling capacitors near each pin is
suggested, such as paralleled 0.1
µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are
also recommended. These supply pins are separated from PLLVDD and AVDD internal to the device
to provide noise isolation. They should be tied at a low impedance point on the circuit board.
FILTER0
FILTER1
54
55
CMOS
I/O
PLL filter pins. These pins are connected to an external capacitance to form a lag-lead filter required
for stable operation of the internal frequency multiplier PLL running off of the crystal oscillator. A
0.1
µF ±10% capacitor is the only external component required to complete this filter.
ISO
23
CMOS
I
Link interface isolation control input. This pin controls the operation of output differentiation logic on
the CTL and D pins. If an optional Annex J type isolation barrier is implemented between the
TSB41LV02A and LLC, the ISO pin should be tied low to enable the differentiation logic. If no
isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the
ISO pin should be tied high to disable the differentiation logic. For additional information refer to TI
application note
Serial Bus Galvanic Isolation, SLLA011.


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