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TSB12LV23PZ Scheda tecnica(PDF) 11 Page - Texas Instruments |
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TSB12LV23PZ Scheda tecnica(HTML) 11 Page - Texas Instruments |
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11 / 85 page  2–3 Table 2–3. PCI System TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PCI_CLK 12 I PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at rising edge of PCLK. G_RST 10 I Global power reset. This reset brings all of the TSB12LV23 to its default state, including those registers not reset by RST. When asserted, the device is completely nonfunctional. PCI_INTA/CINT 8 O Interrupt signal. This output indicates interrupts from the TSB12LV23 to the host. This terminal signals an interrupt based upon the CARDBUS input terminal. RST 76 I PCI or CardBus reset. When this bus reset is asserted, the TSB12LV23 places all output buffers in a high impedance state and resets all internal registers except device power management context- and vendor-specific bits initialized by host power on software. When asserted, the device is completely nonfunctional. Table 2–4. PCI Address and Data TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD PCI_AD0 18 19 21 22 23 25 26 27 31 32 33 34 36 37 38 40 54 56 57 58 59 61 62 64 66 67 68 69 71 72 73 74 I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface during the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 65 53 41 28 I/O PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI terminals. During the address phase of a bus cycle C/BE3–C/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. PCI_PAR 52 I/O PCI parity. In all PCI bus read and write cycles, the TSB12LV23 calculates even parity across the AD and C/BE buses. As an initiator during PCI cycles, the TSB12LV23 outputs this parity indicator with a one PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator; a miscompare can result in a parity error assertion (PERR). |
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