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TSB12LV21 Scheda tecnica(PDF) 7 Page - Texas Instruments |
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TSB12LV21 Scheda tecnica(HTML) 7 Page - Texas Instruments |
7 / 18 page TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE SLLS273 – APRIL 1997 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram Serial EPROM Interface PCI Master PCI Slave Local Bus Interface Logic PCI Configuration Control and Status Registers RAM ROM AUX ZV seeprom_data seeprom_clk pci_ad31 – pci_ad0 pci_cbez3 – pci_cbez0 pci_par pci_framez pci_irdyz pci_trdyz pci_devselz pci_stopz pci_idselz pci_perrz pci_serrz pci_reqz pci_gntz pci_clk pci_resetz pci_intaz 32 / 4 / PCI Bus Logic 4 / 16 / 16 / 2 / 3 / 3 / aux_clk aux_rstz gpio_data3 – gpio_data0 aux_adr15 – aux_adr0 aux_data15 – aux_data0 aux_oez aux_wez1 – aux_wez0 aux_rdy zv_hsync, zv_vsync, zv_pix_clk aux_csz, rom_csz, ram_csz aux_intz zv_data_valid DMA Engine DMA Control and Status Registers DMA Logic General Receiver FIFO Asynchronous Transmit FIFO Isosynchronous Transmit FIFO FIFO Control and Status Registers Pointer Address Mapping Logic FIFO Logic 2 / 8 / phy_ctl0 – phy_ctl1 phy_data0 – phy_data7 phy_clk50 link_cyclein phy_lreq link_cycleout 1394 LLC Control and Status Reg- isters Cycle Timer Cycle Monitor 1394 Packet Transmit Control Logic CRC Logic 1394 Packet Receive Control Logic Phy-Link Interface Logic Parallel-to-Serial Serial-to-Parallel 1394 Link Layer Control (LLC) Logic zv_ext_clk |
Codice articolo simile - TSB12LV21 |
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Descrizione simile - TSB12LV21 |
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