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TSB11LV01 Scheda tecnica(PDF) 11 Page - Texas Instruments |
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TSB11LV01 Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 21 page TSB11LV01 3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION internal register configuration The accessible internal registers of this device are listed in Table 1. Descriptions of the internal register fields are given in Table 2. Table 1. Accessible Internal Registers Address 0 1 2 3 4 5 6 7 0000 Physical ID R CPS 0001 RHB IBR GC 0010 SPD Rev NP 0011 AStat BStat Ch Con Reserved 0100 Reserved 0101 Reserved 0110 Looplnt CPSlnt CPS IR Reserved 0111 Reserved 1000 Reserved Table 2. Internal Register Field Descriptions Field Size (Bits) Type Description AStat 2 Read only AStat contains the line state of TPA. The status is indicated by the following: 11 = Z 01 = 1 10 = 0 00 = Invalid data state. Power-up reset initializes to this line state. This line state is also output dur- ing transmit and receive operations. The line state outputs are generally valid during arbitration and idle conditions on the bus. BStat 2 Read only BStat contains the line state of TPB. The status is indicated by the following: 11 = Z 01 = 1 10 = 0 00 = Invalid data state. Power up reset initializes to this line state. This line state is also output dur- ing transmit and receive operations. The line state outputs are generally valid during arbitration and idle conditions on the bus. Ch 1 Read only When Ch = 1, the port is a child, otherwise it is a parent. This bit is invalid after a hardware reset or a bus reset until tree-ID processing is completed. Con 1 Read only Con indicates the connection status of the port. When Con = 1, the port is connected, otherwise it is disconnected. This bit is set to 1 by a hardware reset and is updated to reflect the actual cable con- nection status of the port during bus reset. The TSB11LV01 contains connection debounce circuitry that prevents a new cable connection on a port from initiating a bus reset until the connection status has been stable for at least 335 ms. Similarly, a cable disconnect must be stable for 1.3 ms before a bus reset is initiated. CPS 1 Read only Cable power status (CPS) contains the status of the CPS input terminal. When cable power voltage has dropped too low for reliable operation, this bit is reset (0). This bit is included twice in the internal registers to expedite handling of the CPSInt. CPSInt 1 Read/Write CPSint indicates that a cable power status interrupt has occurred. This interrupt occurs whenever the CPS input goes low. The interrupt indicates that the cable power voltage has dropped too low to ensure reliable operation. This bit is cleared (0) by a hardware reset or by writing a 0 to this register. However, if the CPS input is still low, another cable power status interrupt immediately occurs. |
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