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TLC2543IN Scheda tecnica(PDF) 10 Page - Texas Instruments |
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TLC2543IN Scheda tecnica(HTML) 10 Page - Texas Instruments |
10 / 27 page TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION Access Cycle B Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Sample Cycle B A/D Conversion Interval Initialize MSB LSB Previous Conversion Data MSB LSB B7 B6 B5 B4 C7 B7 A7 A6 A5 A4 A3 A2 A1 A0 12 3 4 5 6 7 8 1 I/O CLOCK DATA OUT DATA INPUT CS EOC Initialize Hi-Z (see Note A) B3 B2 B1 B0 tconv NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS ↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 11. Timing for 8-Clock Transfer Using CS With MSB First Access Cycle B Sample Cycle B A/D Conversion Interval Initialize MSB LSB Previous Conversion Data MSB LSB B7 B6 B5 B4 C7 B7 A7 A6 A5 A4 A3 A2 A1 A0 Low Level 12 3 4 5 6 7 8 1 I/O CLOCK DATA OUT DATA INPUT CS EOC Initialize (see Note A) B3 B2 B1 B0 tconv Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS ↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First |
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