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TLC2551IDGK Scheda tecnica(PDF) 7 Page - Texas Instruments |
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TLC2551IDGK Scheda tecnica(HTML) 7 Page - Texas Instruments |
7 / 23 page TLC2551, TLC2552, TLC2555 5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS276 –MARCH 2000 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing diagrams/conversion cycles (continued) OD8 SCLK 1 2 3 4 5 6 12 13 14 15 16 CS/FS OD7 OD6 OD5 OD0 SDO t(sample) tc t(powerdown) 7 OD9 1 OD10 OD9 OD11 OD10 OD11 Figure 5. TLC2555 Timing use CS as FS input When interfacing the TLC2551 with the TMS320 DSP, the FSR signal from the DSP may be connected to the CS input if this is the only device on the serial port. This will save one output terminal from the DSP. (Output data changes on the falling edge of SCLK. Default for TLC2552 and TLC2555). SCLK and conversion speed It takes 14 conversion clocks to complete the conversion. The conversion clock for the TLC2551/2/5 is equal to SCLK/2. This yields a minimum conversion time of 1.4 µs plus 0.1 µs overhead. These devices can operate with an SCLK up to 20 MHz for the supply voltage range specified. The total conversion time is 14 × (1/10M) +16 × (1/20M)+ 0.1 µs} = 2.3 µs for a 20 MHz SCLK. This is the minimum cycle time for an active CS or CS/FS signal. If violated, the conversion will terminate, invalidating the next data output cycle. reference voltage An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of the analog inputs to produce a full-scale reading. The value of VREF and the analog input should not exceed the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal to or lower than GND. powerdown and powerup initialization Autopower down is built in to the devices in order to reduce power consumption. The wake-up time is fast enough to provide power down between each cycle. The power-down state is initiated at the end of conversion and wakes up upon a falling edge on CS or FS. |
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