TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043C – MAY 1991 – REVISED MARCH 1995

2–8

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

The operating sequence for complete data acquisition is shown in Figure 3. Processors can address the TLC1550

and TLC1551 as an external memory device by simply connecting the address lines to a decoder and the decoder

output to CS. Like other peripheral devices, the write (WR) and read (RD) input signals are valid only when CS is low.

Once CS is low, the on-board system clock permits the conversion to begin with a simple write command and the

converted data to be presented to the data bus with a simple read command. The device remains in a sampling (track)

mode from the rising edge of EOC until conversion begins with the rising edge of WR, which initiates the hold mode.

After the hold mode begins, the clock controls the conversion automatically. When the conversion is complete, the

end-of-conversion (EOC) signal goes low indicating that the digital data has been transferred to the output latch.

Lowering CS and RD then resets EOC and transfers the data to the data bus for the processor read cycle.

0.8 V

0.8 V

0.8 V

0.8 V

1.4 V

2 V

1.4 V

0.8 V

2 V

0.8 V

2 V

0.8 V

2 V

0.8 V

tsu(CS)

th(CS)

tw(WR)

tconv

tsu(CS)

th(CS)

tdis(D)

tv(D)

ta(D)

td(EOC)

0.8 V

2 V

CS

WR

RD

EOC

D0 – D9

Data Valid

Figure 3. TLC1550 or TLC1551 Operating Sequence