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TL16C750PM Scheda tecnica(PDF) 10 Page - Texas Instruments |
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TL16C750PM Scheda tecnica(HTML) 10 Page - Texas Instruments |
10 / 35 page TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 system timing requirements over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tcR Cycle time, read (tw7 + td8 + td9) RC 87 ns tcW Cycle time, write (tw6 + td5 + td6) WC 87 ns tw1 Pulse duration, clock (XIN) high tXH 4 f = 16 MHz maximum 25 ns tw2 Pulse duration, clock (XIN) low tXL 4 f = 16 MHz maximum 25 ns tw5 Pulse duration, ADS low tADS 5, 6 9 ns tw6 Pulse duration, write strobe tWR 5 40 ns tw7 Pulse duration, read strobe tRD 6 40 ns tw8 Pulse duration, MR tMR 1 µs tsu1 Setup time, address valid before ADS ↑ tAS 5, 6 8 ns tsu2 Setup time, CS valid before ADS ↑ tCS 5, 6 8 ns tsu3 Setup time, data valid before WR1 ↓ or WR2↑ tDS 5 15 ns tsu4† Setup time, CTS↑ before midpoint of stop bit 16 10 ns th1 Hold time, address low after ADS ↑ tAH 5, 6 0 ns th2 Hold time, CS valid after ADS ↑ tCH 5, 6 0 ns th3 Hold time, CS valid after WR1 ↑ or WR2↓ tWCS 5 10 ns th4† Hold time, address valid after WR1 ↑ or WR2↓ tWA 5 10 ns th5 Hold time, data valid after WR1 ↑ or WR2↓ tDH 5 5 ns th6 Hold time, CS valid after RD1 ↑ or RD2↓ tRCS 6 10 ns th7† Hold time, address valid after RD1 ↑ or RD2↓ tRA 6 20 ns td4† Delay time, CS valid before WR1 ↓ or WR2↑ tCSW 5 7 ns td5 Delay time, address valid before WR1 ↓ or WR2↑ tAW 5 7 ns td6† Delay time, write cycle, WR1 ↑ or WR2↓ to ADS↓ tWC 5 40 ns td7† Delay time, CS valid to RD1 ↓ or RD2↑ tCSR 6 7 ns td8† Delay time, address valid to RD1 ↓ or RD2↑ tAR 6 7 ns td9 Delay time, read cycle, RD1 ↑ or RD2↓ to ADS↓ tRC 6 40 ns td10 Delay time, RD1 ↓ or RD2↑ to data valid tRVD 6 CL = 75 pF 45 ns td11 Delay time, RD1 ↑ or RD2↓ to floating data tHZ 6 CL = 75 pF 20 ns † Only applies when ADS is low system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 9) PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tdis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ tRDD 6 CL = 75 pF 20 ns NOTE 9: Charge and discharge times are determined by VOL, VOH, and external loading. baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tw3 Pulse duration, BAUDOUT low tLW 4 f = 16 MHz, CLK ÷ 2 50 ns tw4 Pulse duration, BAUDOUT high tHW 4 f = 16 MHz, CLK ÷ 2 50 ns td1 Delay time, XIN ↑ to BAUDOUT↑ tBLD 4 45 ns td2 Delay time, XIN ↑↓ to BAUDOUT↓ tBHD 4 45 ns |
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