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SN74TVC3010PW Scheda tecnica(PDF) 6 Page - Texas Instruments |
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SN74TVC3010PW Scheda tecnica(HTML) 6 Page - Texas Instruments |
6 / 11 page SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION TVC voltage-limiting application For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any one of the transistors (see Figure 3). This connection determines the VBIAS input of the reference transistor. The VBIAS input is connected through a pullup resistor (typically, 200 kΩ ) to the VDD supply. A filter capacitor on VBIAS is recommended. The opposite side of the reference transistor is used as the reference voltage (VREF) connection. The VREF input must be less than VDD – 1 V to bias the reference transistor into conduction. The reference transistor regulates the gate voltage (VG) of all the pass transistors. VG is determined by the characteristic gate-to-source voltage difference (VGS) because VG = VREF + VGS. The low-voltage side of the pass transistors has a high-level voltage limited to a maximum of VG – VGS, or VREF. 200 k Ω 3.3 V 150 Ω 150 Ω 150 Ω 150 Ω Open-Drain CPU Interface Motherboard Interface 34 5 24 46 45 44 25 1 2.5 V TVC16222 GATE† 48 B1 (VBIAS)† 47 2 A1 (VREF)† † VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to VBIAS. Figure 3. Typical Application Circuit |
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