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AD7846AQ Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD7846AQ Scheda tecnica(HTML) 8 Page - Analog Devices |
8 / 16 page REV. E –8– AD7846 S1 VREF+ VREF– DAC1 DB15–DB12 DB15–DB12 SEGMENT 1 SEGMENT 16 S3 S15 S17 S16 S14 S4 S2 DAC2 DAC3 12 BIT DAC DB11–DB0 R R VOUT RIN A3 A2 A1 Figure 16. D/A Conversion Output Stage The output stage of the AD7846 is shown in Figure 17. It is capable of driving a 2 k Ω/1000 pF load. It also has a resistor feedback network which allows the user to configure it for gains of one or two. Table I shows the different output ranges that are possible. An additional feature is that the output buffer is configured as a track-and-hold amplifier. Although normally tracking its input, this amplifier is placed in a hold mode for approximately 2.5 µs after the leading edge of LDAC. This short state keeps the DAC output at its previous voltage while the AD7846 is internally changing to its new value. So, any glitches that occur in the transition are not seen at the output. In systems where the LDAC is tied permanently low, the deglitching will not be in operation. Figures 8 and 9 show the outputs of the AD7846 without and with the deglitcher. C1 LDAC VOUT RIN DAC3 ONE SHOT 10k 10k Figure 17. Output Stage UNIPOLAR BINARY OPERATION Figure 18 shows the AD7846 in the unipolar binary circuit configuration. The DAC is driven by the AD586, +5 V refer- ence. Since RIN is tied to 0 V, the output amplifier has a gain of 2 and the output range is 0 V to +10 V. If a 0 V to +5 V range is required, RIN should be tied to VOUT, configuring the output stage for a gain of 1. Table III gives the code table for the circuit of Figure 18. RIN VOUT DGND +15V +5V VCC VDD VREF+ VREF– R1 10k C1 1 F SIGNAL GROUND –15V *ADDITIONAL PINS OMITTED FOR CLARITY AD7846* AD586 VOUT (0V TO +10V) VSS 4 Figure 18. Unipolar Binary Operation Table III. Code Table for Figure 18 Binary Number Analog Output in DAC Latch (VOUT) MSB LSB 1111 1111 1111 1111 +10 (65535/65536) V 1000 0000 0000 0000 +10 (32768/65536) V 0000 0000 0000 0001 +10 (1/65536) V 0000 0000 0000 0000 0 NOTE 1 LSB = 10 V/2 16 = 10 V/65536 = 152 µV. Offset and gain may be adjusted in Figure 18 as follows: To adjust offset, disconnect the VREF– input from 0 V, load the DAC with all 0s and adjust the VREF– voltage until VOUT = 0 V. For gain adjustment, the AD7846 should be loaded with all 1s and R1 adjusted until VOUT = 10 (65535)/(65536) = 9.999847 V. If a simple resistor divider is used to vary the VREF– voltage, it is important that the temperature coefficients of these resistors match that of the DAC input resistance (–300 ppm/ °C). Other- wise, extra offset errors will be introduced over temperature. Many circuits will not require these offset and gain adjustments. In these circuits, R1 can be omitted. Pin 5 of the AD586 may be left open circuit and Pin 8 (VREF– ) of the AD7846 tied to 0 V. |
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