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SN74ALVCH162836 Scheda tecnica(PDF) 1 Page - Texas Instruments |
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SN74ALVCH162836 Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 10 page SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122E – JULY 1997 – REVISED JUNE 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Member of the Texas Instruments Widebus ™ Family D EPIC ™ (Enhanced-Performance Implanted CMOS) Submicron Process D Output Port Has Equivalent 26-Ω Series Resistors, So No External Resistors Are Required D Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 250 mA Per JESD 17 D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR. description This 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The output port includes equivalent 26- Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162836 is characterized for operation from –40 °C to 85°C. Copyright © 1999, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DGG, DGV, OR DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OE Y1 Y2 GND Y3 Y4 VCC Y5 Y6 Y7 GND Y8 Y9 Y10 Y11 Y12 Y13 GND Y14 Y15 Y16 VCC Y17 Y18 GND Y19 Y20 NC CLK A1 A2 GND A3 A4 VCC A5 A6 A7 GND A8 A9 A10 A11 A12 A13 GND A14 A15 A16 VCC A17 A18 GND A19 A20 LE NC – No internal connection EPIC and Widebus are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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