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SN74ALS236FN Scheda tecnica(PDF) 4 Page - Texas Instruments |
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SN74ALS236FN Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 11 page SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing diagram RST SI D3 – D0 SO Q3 – Q0 IR OR W1 Don’t Care Word 1 Word 2 Invalid† Word 1‡ Word 2 Word 3 Clear Shift In W1 Shift Out W2 Empty Full W2 W1 W2 W63 W64 W1 † The last data word shifted out of the FIFO remains at the output until a new word falls through or an RST pulse clears the FIFO. ‡ While the output data is considered valid only when the OR flag is high, the stored data remains at the outputs. Any additional words written into the FIFO stack up behind the first word and do not appear at the output until SO is taken low. |
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