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SN74AS804BDWE4 Scheda tecnica(PDF) 1 Page - Texas Instruments |
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SN74AS804BDWE4 Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 13 page SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS SDAS022C – DECEMBER 1982 – REVISED JANUARY 1995 Copyright © 1995, Texas Instruments Incorporated 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 • High Capacitive-Drive Capability • ′ALS804A Has Typical Delay Time of 4 ns (CL = 50 pF) and Typical Power Dissipation of 3.4 mW Per Gate • ′AS804B Has Typical Delay Time of 2.6 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 9 mW Per Gate • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description These devices contain six independent 2-input NAND drivers. They perform the Boolean functions Y = A • B or Y = A + B in positive logic. The SN54ALS804A and SN54AS804B are characterized for operation over the full military temperature range of – 55 °C to 125°C. The SN74ALS804A and SN74AS804B are characterized for operation from 0 °C to 70°C. FUNCTION TABLE (each driver) INPUTS OUTPUT A B Y H H L L XH X L H logic symbol† logic diagram (positive logic) 1 1A 2 1B 4 2A 5 2B 7 3A 8 3B 12 4A 13 4B & 1Y 3 2Y 6 3Y 9 4Y 11 15 5A 16 5B 18 6A 19 6B 5Y 14 6Y 17 1Y 3 1 1A 2 1B 2Y 6 4 2A 5 2B 3Y 9 7 3A 8 3B 4Y 11 12 4A 13 4B 5Y 14 15 5A 16 5B 6Y 17 18 6A 19 6B † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1A 1B 1Y 2A 2B 2Y 3A 3B 3Y GND VCC 6B 6A 6Y 5B 5A 5Y 4B 4A 4Y SN54ALS804A, SN54AS804B ...J PACKAGE SN74ALS804A, SN74AS804B . . . DW OR N PACKAGE (TOP VIEW) 3 2 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 6A 6Y 5B 5A 5Y 2A 2B 2Y 3A 3B SN54ALS804A, SN54AS804B . . . FK PACKAGE (TOP VIEW) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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