SN54ALS299, SN74ALS299

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

WITH 3-STATE OUTPUTS

SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994

5

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

SN54ALS299

SN74ALS299

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency (at 50% duty cycle)

0

17

0

30

MHz

t

Pulse duration

CLK high or low

22

16.5

ns

tw

Pulse duration

CLR low

12

10

ns

↑

S0 or S1

25

20

t

Setup time before CLK

↑

Serial or parallel data

High

18

16

ns

tsu

Serial or parallel data

Low

15

6

ns

Inactive-state setup time before CLK

↑†

CLR

15

15

th

Hold time after CLK

↑

S0 or S1

0

0

ns

th

Hold time after CLK

↑

Serial or parallel data

0

0

ns

† Inactive-state setup time is also referred to as recovery time.

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

R1 = 500

R2 = 500

TA = MIN to MAX‡

UNIT

SN54ALS299

SN74ALS299

MIN

MAX

MIN

MAX

fmax

17

30

MHz

tPLH

CLK

QQ

2

19

4

13

ns

tPHL

CLK

QA– QH

4

25

7

19

ns

tPLH

CLK

Q

′ or Q ′

2

21

5

15

ns

tPHL

CLK

QA

′ or QH′

4

25

8

18

ns

tPHL

CLR

QA –QH

6

29

6

22

ns

tPHL

CLR

QA

′ or QH′

6

29

6

22

ns

tPZH

OE1 OE2

QQ

5

22

6

16

ns

tPZL

OE1, OE2

QA – QH

6

27

8

22

ns

tPZH

S0 S1

QQ

5

27

7

17

ns

tPZL

S0, S1

QA – QH

6

26

8

22

ns

tPHZ

OE1 OE2

QQ

1

15

1

8

ns

tPLZ

OE1, OE2

QA – QH

4

38

5

15

ns

tPHZ

S0 S1

QA QH

1

16

1

12

ns

tPLZ

S0, S1

QA – QH

4

34

8

25

ns

‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.