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SN74AS109AN Scheda tecnica(PDF) 5 Page - Texas Instruments |
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SN74AS109AN Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 9 page SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† UNIT (INPUT) (OUTPUT) SN54AS109A SN74AS109A MIN MAX MIN MAX fmax* 90 105 MHz tPLH PRE or CLR QorQ 2 9 2 8 ns tPHL PRE or CLR Q or Q 3.5 11.5 3.5 10.5 ns tPLH CLK QorQ 2.5 10 2.5 9 ns tPHL CLK Q or Q 3.5 10.5 3.5 9 ns * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. |
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