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SN74ABT646DGVRE4 Scheda tecnica(PDF) 3 Page - Texas Instruments |
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SN74ABT646DGVRE4 Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 16 page SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E – JULY 1991 – REVISED JULY 1994 2–3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS DATA I/Os OPERATION OR FUNCTION OE DIR CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8 OPERATION OR FUNCTION X X ↑ X X X Input Unspecified† Store A, B unspecified† X XX ↑ X X Unspecified† Input Store B, A unspecified† H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus † The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs. logic symbol‡ OE G3 21 3 EN2 [AB] G5 22 SBA A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 A8 11 A1 4 B1 20 4D B2 19 B3 18 B4 17 B5 16 B6 15 B7 14 B8 13 3 EN1 [BA] 3 DIR 23 CLKBA 1 CLKAB G7 2 SAB 5 7 7 5 1 1 6D ≥1 ≥1 1 2 C6 C4 ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, and PW packages. |
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