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74FCT162646ATPACT Scheda tecnica(PDF) 6 Page - Texas Instruments |
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74FCT162646ATPACT Scheda tecnica(HTML) 6 Page - Texas Instruments |
6 / 9 page CY74FCT16646T CY74FCT162646T 6 Switching Characteristics Over the Operating Range[15] Parameter Description CY74FCT16646T CY74FCT16646AT CY74FCT162646AT Unit Min. Max. Min. Max. Fig. No.[16] tPLH tPHL Propagation Delay Bus to Bus 1.5 9.0 1.5 6.3 ns 1, 2 tPZH tPZL Output Enable Time DIR or OE to Bus 1.5 14.0 1.5 9.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time DIR or OE to Bus 1.5 9.0 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 9.0 1.5 6.3 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to Bus 1.5 11.0 1.5 7.7 ns 1,5 tSU Set-Up Time HIGH or LOW Bus to Clock 2.0 — 2.0 — ns 4 tH Hold Time HIGH or LOW Bus to Clock 1.5 — 1.5 — ns 4 tW Clock Pulse Width HIGH or LOW 5.0 — 5.0 — ns 6 tSK(O) Output Skew[17] — 0.5 — 0.5 ns — Parameter Description CY74FCT16646CT CY74FCT162646CT CY74FCT16646ET CY74FCT162646ET Unit Min. Max. Min. Max. Fig. No.[16] tPLH tPHL Propagation Delay Bus to Bus 1.5 5.4 1.5 3.8 ns 1, 2 tPZH tPZL Output Enable Time DIR or OE to Bus 1.5 7.8 1.5 4.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time DIR or OE to Bus 1.5 6.3 1.5 4.0 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 5.7 1.5 3.8 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to Bus 1.5 6.2 1.5 4.2 ns 1,5 tSU Set-Up Time HIGH or LOW Bus to Clock 2.0 — 2.0 — ns 4 tH Hold Time HIGH or LOW Bus to Clock 1.5 — 0.0 — ns 4 tW Clock Pulse Width HIGH or LOW 5.0 — 3.0 — ns 6 tSK(O) Output Skew[17] — 0.5 — 0.5 ns — Notes: 15. Minimum limits are specified but not tested on Propagation Delays. 16. See “Parameter Measurement Information” in the General Information section. 17. Skew any two outputs of the same package switching in the same direction. This parameter is ensured by design. |
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