CDCF2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS628B – APRIL 1999 REVISED NOVEMBER 1999

7

POST OFFICE BOX 655303

TYPICAL CHARACTERISTICS

0

5

10

15

20

25

30

35

40

45

50

C(LF) – Lumped Feedback Capacitance at FBIN – pF

10

0

–10

–20

20

–30

–40

100

0

–300

200

–400

Phase Error

Phase Adjustment Slope

–100

–200

VCC = 3.3 V

fc = 133 MHz

C(LY) = 25pF

TA = 25°C

See Notes A and B

PHASE ADJUSTMENT SLOPE AND PHASE ERROR

vs

LOAD CAPACITANCE

Figure 3

NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω Phase error measured from CLK to Y

B. CLF = Lumped feedback capacitance at FBIN

Figure 4

PHASE ERROR

vs

CLOCK FREQUENCY

50

60

70

80

90

100 110

120

fc – Clock Frequency – MHz

–100

–150

–250

–300

–350

–400

–200

–50

0

–450

–500

VCC = 3.3 V

C(LY) = 25 pF

C(LF) = 12 pF

TA = 25°C

See Note A

130

140

Figure 5

PHASE ERROR

vs

SUPPLY VOLTAGE

–100

–150

–250

–300

–350

–400

–200

3.1

3.2

3.3

3.4

3.5

–50

0

–450

–500

VCC – Supply Voltage – V

3.6

3

fc = 133 MHz

C(LY) = 25 pF

C(LF) = 12 pF

TA = 25°C

See Note A

NOTE A: Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω