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MC-ACT-UARTM-VHDL Scheda tecnica(PDF) 7 Page - Actel Corporation |
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MC-ACT-UARTM-VHDL Scheda tecnica(HTML) 7 Page - Actel Corporation |
7 / 9 page Verification and Compliance Functional and timing simulation has been performed on the MultiChannel UART using a self-checking Verilog Test Bench with Verilog test cases. Timing Read and Write cycles have a recovery time due to time slicing latency. The recovery time is (3 * NUM_CHANNELS+3)*tCY , where tCY is the cycle time of the input clock. However, if a FIFO Read immediately follows a FIFO Read, the recovery time is 4*tCY. If a FIFO Write immediately follows a FIFO Write, the recovery time is 4*tCY. The timing diagrams below reflect ads_n held active, or low. Since this IP is a core, the effects of part speed grade, family, routing variations, and effects of user logic in placement and routing will have varying degrees of impact on the timing. The user must take these things in consideration to insure a successful implementation. The Timing information provided in this document, will ad- dress timing requirements based upon architectural aspects of this IP only. READ TIMING The figure below shows the setup times required for a successful read. It also shows the expected delay between the assertion of the rd_n signal, and valid data on the bus. The data remains valid as long as A, cs_n, and rd_n are held in their active states. Figure 3: Asynchronous Timing For Reads Description Min Max tSUCS Setup time for cs_n with respect to rd_n tCY tSUA Setup time for A with repect to rd_n tCY tHCS Hold time for CS with respect to rd_n tCY tHA Hold time for A with respect to rd_n NUM_CHANNELS*tCY tDV3 Delay between rd_n assertion (going low) and valid data on the bus 2*tCY tRD3 rd_n strobe width 2*tCY trecovery1,2 Delay from previous rd_n or wr_n rising edge to the falling edge of rd_n (3* NUM_CHANNELS+3)*tCY Table 4: Read Timing Descriptions Where: • NUM_CHANNELS is the number of ports selected of the implementation • tCY is the period of the system clock • 1 A Read FIFO followed by a Read FIFO of the same channel requires a recovery time (trecovery) of a minimum of 4*tCY . • 2 A Write MCR followed by a Read MSR with MCR[4] (Loop) equal 1, requires a recovery time of (8 * NUM_CHANNELS+3)* tCY. • 3 The rd_n input signal is sampled a minimum of 2 times by the clock. If the host interface is not synchronous to the rising edge of the clock, increase the width of the rd_n signal accordingly. cs_n rd_n data_out A Data Valid t DV t SUCS t SUA wr_n t recovery 1,2 t RD t HCS t HA |
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