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MC-ACT-UL3LINK-VHDL Scheda tecnica(PDF) 2 Page - Actel Corporation

Il numero della parte MC-ACT-UL3LINK-VHDL
Spiegazioni elettronici  Function compatible with ATM Forum Asynchronous/synchronous FIFO using RAM
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Produttore elettronici  ACTEL [Actel Corporation]
Homepage  http://www.actel.com
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MC-ACT-UL3LINK-VHDL Scheda tecnica(HTML) 2 Page - Actel Corporation

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Functional Description
This core conforms to the appropriate standard(s). In general, standards do not define the internal user interface, only the external interfaces and protocols. There-
fore, Avnet Memec has created a simple FIFO interface to this core for easy user connectivity. This document describes this Avnet Memec created interface. Please
consult the appropriate standards document for all external signaling.
TOP_MASTER
This is the top level of the core. Its only purpose is to serve as a container to instantiate the Ingress and Egress modules.
Egress Master
The egress master is responsible for polling the PHYs and internal queues in order to send cells to the slave device.
Ingress/Egress FIFO
The FIFO contains the RAM FIFO and the pointer processing blocks. The FIFO operates in synchronous and asynchronous systems. The FIFO contains additional
logic to implement a SOC-SOC pointer reset. There is one FIFO per PHY polled.
Ingress Master
The Ingress master is responsible for polling the PHYs and internal queues in order to accept cells from the slave device.
Figure 1: Logic Symbol
MDS8074a
rd_enb
rd_data
rd_flag
rd_clk
wr_enb
wr_data
wr_flag
wr_clk
txclk
tx_data
txenb_n
txclav
tx_soc
txprty
tx_addr
reset_n
fifo_16/fifo_8
top_egr_master
egr_utopia_mast
er
top_egr_master
ing_utopia_master
top_ing_master
fifo_16/fifo_8
top_ing_master
rxclk
rx_data
rxenb_n
rx_clav
rx_prty
rx_soc
rx_addr


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