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TC660CPA Scheda tecnica(PDF) 5 Page - TelCom Semiconductor, Inc |
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TC660CPA Scheda tecnica(HTML) 5 Page - TelCom Semiconductor, Inc |
5 / 8 page 4-9 TELCOM SEMICONDUCTOR, INC. 7 6 5 4 3 1 2 8 TC660 100mA CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER Figure 1. TC660 Test Circuit (Inverter) Figure 2. Idealized Switched Capacitor V+ GND S3 S1 S2 S4 C2 VOUT = – VIN C1 Theoretical Power Efficiency Considerations In theory, a voltage multiplier can approach 100% efficiency if certain conditions are met: (1) The drive circuitry consumes minimal power. (2) The output switches have extremely low ON resistance and virtually no offset. (3) The impedances of the pump and reservoir capacitors are negligible at the pump frequency. The TC660 approaches these conditions for negative voltage multiplication if large values of C1 and C2 are used. Energy is lost only in the transfer of charge between capacitors if a change in voltage occurs. The energy lost is defined by: E = 1/2 C1 (V1 2 – V 2 2) V1 and V2 are the voltages on C1 during the pump and transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (refer to Figure 2) compared to the value of RL, there will be a substantial difference in voltages V1 and V2. Therefore, it is desirable not only to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation. 1 2 3 4 8 7 6 5 TC660 + V+ (+5V) VOUT C1 150 µF + C2 150 µF IL RL IS V+ Circuit Description The TC660 contains all the necessary circuitry to com- plete a voltage inverter (Figure 1), with the exception of two external capacitors, which may be inexpensive 150 µF polar- ized electrolytic capacitors. Operation is best understood by considering Figure 2, which shows an idealized voltage inverter. Capacitor C1 is charged to a voltage V + for the half cycle when switches S1 and S3 are closed. (Note: Switches S2 and S4 are open during this half cycle.) During the second half cycle of operation, switches S2 and S4 are closed, with S1 and S3 open, thereby shifting capacitor C1 negatively by V + volts. Charge is then transferred from C 1 to C2, such that the voltage on C2 is exactly V +, assuming ideal switches and no load on C2. The four switches in Figure 2 are MOS power switches; S1 is a P-channel device, and S2, S3 and S4 are N-channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S3 and S4 must always remain reverse-biased with respect to their sources, but not so much as to degrade their ON resistances. In addition, at circuit start-up, and under output short circuit conditions (VOUT = V +), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and possible device latch-up. This problem is eliminated in the TC660 by a logic network which senses the output voltage (VOUT) together with the level translators, and switches the substrates of S3 and S4 to the correct level to maintain necessary reverse bias. To improve low-voltage operation, the “LV” pin should be connected to GND, disabling the internal regulator. For supply voltages greater than 3.0V, the LV terminal should be left open to ensure latch-up-proof operation and prevent device damage. |
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