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STC3500 Scheda tecnica(PDF) 10 Page - Connor-Winfield Corporation |
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STC3500 Scheda tecnica(HTML) 10 Page - Connor-Winfield Corporation |
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10 / 48 page  Preliminary Data Sheet: TM060 Page 10 of 48 Rev: P06 Date: 11/22/04 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Detailed Description continued Master/Slave Operation Pairs of STC3500 devices may be operated in a master/slave configuration for added reliability. A typical configuration is shown below: Master / Slave Configuration Figure 2 STC3500 STC3500 Sync_8K or Sync_Clk Sync_8K or Sync_Clk Ref In Ref In Xref 2 STC3500 1 Xref The Sync_8K or Sync_Clk output of each device is cross-connected to the other device’s Xref input. The device auto- detects the frequency on the Xref input. Master or slave state of a device is determined by the M/S pin. Thus, master/ slave state is always manually controlled by the application. The master synchronizes to the selected input reference, while the slave synchronizes to the Xref input. (Note that 8 kHz frame phase alignment is maintained across a master/ slave pair of devices only if Sync_8K is used as the cross couple signal.) The unit operating in slave mode locks on and phase-aligns to the cross-reference clock (Sync_8K or Sync_Clk) from the unit in master mode. The phase skew between the input cross-reference and the output clock for the slave unit is typically less than ±1ns (under ±3ns in dynamic situations, including reference jitter and wander). Perfect phase alignment of the two Sync_Clk output clocks would require no delay on the cross-reference clock connection. To accommodate path length delays, the STC3500 provides a programmable phase skew feature. The slave’s Sync_Clk/8k output may be phase shifted -32nS to +31.75nS relative to Xref according to the contents of the Phase_Offset register to compensate for the path length of the Sync_8K or Sync_Clk to Xref connection. This offset may therefore be programmed to exactly compensate for the actual path length delay associated with the particular application’s cross-reference traces. The offset may further be adjusted to accommodate any output clock distribution path delay differences. Thus, master/slave switches with the STC3500 devices may be accomplished with near-zero phase hits. The first time a unit becomes a slave, such as immediately after power-up, its output clock phase starts out arbitrary, and will quickly phase-align to the cross-reference from the master unit. The phase skew will be eliminated (or converged to the programmed phase offset) step by step. The whole pull-in-and-lock process will complete in about 60 seconds. There is no frequency slew protection in slave mode. In slave mode, the unit’s mission is to lock to and follow the master. Once a pair of units has been operating in aligned master/slave mode, and a master/slave switch occurs, the unit that becomes master will maintain its output clock phase and frequency while a phase build-out (to the current output clock phase) is performed on its selected reference input. Therefore, as master mode operation commences, there will be no phase or frequency hits on the clock output. Likewise, the unit that becomes the slave will maintain its output clock frequency and phase for 1 msec before starting to follow the cross-reference, protecting the downstream clock users during the switch. Assuming the phase offset is programmed for the actual propagation delay of this cross-reference path, there will again be no phase hits on the output clock of the unit that has transitioned from master to slave. |
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