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TL28L92FR Scheda tecnica(PDF) 2 Page - Texas Instruments |
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TL28L92FR Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 61 page Contents TL28L92 3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008 www.ti.com 1 General Description .............................................................................................................. 5 1.1 Features ....................................................................................................................... 5 1.2 Description .................................................................................................................... 5 1.2.1 Device Information ........................................................................................................... 7 2 Functional Description ........................................................................................................ 15 2.1 Block Diagram .............................................................................................................. 15 2.1.1 Data Bus Buffer .................................................................................................. 15 2.1.2 Operation Control ................................................................................................ 15 2.1.3 Interrupt Control ................................................................................................. 15 2.1.4 FIFO Configuration .............................................................................................. 15 2.1.5 68xxx Mode ...................................................................................................... 15 2.2 Timing Circuits .............................................................................................................. 16 2.2.1 Crystal Clock ..................................................................................................... 16 2.2.2 Baud Rate Generator ........................................................................................... 16 2.2.3 Counter/Timer .................................................................................................... 16 2.2.4 Timer Mode ....................................................................................................... 16 2.2.5 Counter Mode .................................................................................................... 17 2.2.6 Time-Out Mode .................................................................................................. 17 2.2.7 Time-Out Mode Caution ........................................................................................ 18 2.2.8 Communications Channels A and B .......................................................................... 18 2.2.9 Input Port ......................................................................................................... 18 2.2.10 Output Port ....................................................................................................... 19 2.3 Operation .................................................................................................................... 19 2.3.1 Transmitter ....................................................................................................... 19 2.3.2 Receiver .......................................................................................................... 20 2.3.3 Transmitter Reset and Disable ................................................................................ 20 2.3.4 Receiver FIFO ................................................................................................... 20 2.3.5 Receiver Status Bits ............................................................................................. 20 2.3.6 Receiver Reset and Disable ................................................................................... 21 2.3.7 Watchdog ......................................................................................................... 21 2.3.8 Receiver Time-Out Mode ...................................................................................... 21 2.3.9 Time-Out Mode Caution ........................................................................................ 22 2.3.10 Multi-Drop Mode (9-Bit or Wake-Up) .......................................................................... 22 3 Programming ..................................................................................................................... 23 3.1 Register Overview .......................................................................................................... 23 3.2 Condensed Register Bit Formats ........................................................................................ 24 3.3 Register Descriptions ...................................................................................................... 26 3.3.1 Mode Registers .................................................................................................. 26 3.3.1.1 Mode Register 0 Channel A (MR0A) ............................................................... 26 3.3.1.2 Mode Register 1 Channel A (MR1A) ............................................................... 27 3.3.1.3 Mode Register 2 Channel A (MR2A) ............................................................... 28 3.3.1.4 Mode Register 0 Channel B (MR0B) ............................................................... 31 3.3.1.5 Mode Register 1 Channel B (MR1B) ............................................................... 31 3.3.1.6 Mode Register 2 Channel B (MR2B) ............................................................... 31 3.3.2 Clock Select Registers .......................................................................................... 31 3.3.2.1 Clock Select Register Channel A (CSRA) ......................................................... 31 3.3.2.2 Clock Select Register Channel B (CSRB) ........................................................ 33 3.3.3 Command Registers ............................................................................................ 33 3.3.3.1 Command Register Channel A (CRA) ............................................................. 33 3.3.3.2 Command Register Channel B (CRB) ............................................................ 34 Contents 2 Submit Documentation Feedback |
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