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CS42432-CMZ Scheda tecnica(PDF) 9 Page - Cirrus Logic |
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CS42432-CMZ Scheda tecnica(HTML) 9 Page - Cirrus Logic |
9 / 58 page DS673F2 9 CS42432 2. PIN DESCRIPTIONS - HARDWARE MODE Pin Name # Pin Description TEST 1,2,4 Test (Input) - Must be tied high or low. Do not leave unconnected. MFREQ 3 MCLK Frequency (Input) - Sets the required frequency range of the input Master Clock. See sec- tion 5.4 for the appropriate settings. RST 5 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. VLC 6 Control Port Power (Input) - Determines the required signal level for the control port interface. See “Digital I/O Pin Characteristics” on page 8. FS 7 Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD 8 Digital Power (Input) - Positive power supply for the digital section. VLS 10 Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter- faces. SCLK 11 Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256xFs. ADC_SDOUT 13 Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data. DAC_SDIN 14 DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data. AUX_LRCK 15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. AUX_SDIN 17 Auxiliary Serial Input (Input) - The 42432 provides an additional serial input for two’s comple- ment serial audio data. TEST 6 2 4 8 10 1 3 5 7 9 11 12 14 15 16 17 18 19 20 21 22 23 24 25 33 37 35 31 29 38 36 34 32 30 28 27 52 51 50 49 48 47 46 45 44 43 42 41 VLS FS MCLK VLC TEST TSTO AOUT5+ AGND VA ADC_SDOUT MFREQ RST AOUT6+ DGND VD SCLK VQ AOUT6- 13 TEST 26 39 AOUT5- 40 TSTO TSTO TSTO AIN1+ AIN1- CS42432 |
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