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CS5340-DZZ Scheda tecnica(PDF) 1 Page - Cirrus Logic

Il numero della parte CS5340-DZZ
Spiegazioni elettronici  101 dB, 192 kHz, Multi-Bit Audio A/D Converter
Download  22 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5340-DZZ Scheda tecnica(HTML) 1 Page - Cirrus Logic

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Copyright
© Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
101 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture
24-bit Conversion
Supports All Audio Sample Rates Including
192 kHz
101 dB Dynamic Range at 5 V
-94 dB THD+N
90 mW Power Consumption
High-Pass Filter to Remove DC Offsets
Analog/Digital Core Supplies from 3.3 V to 5 V
Supports Logic Levels between 1.8 V and 5 V
Auto-detect Mode Selection in Slave Mode
Auto-Detect MCLK Divider
Pin Compatible with CS5341
General Description
The CS5340 is a complete analog-to-digital converter
for digital audio systems. It performs sampling, analog-
to-digital conversion, and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form
at sample rates up to 200 kHz per channel.
The CS5340 uses a 5th-order, multi-bit Delta-Sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The CS5340 is available in a 16-pin TSSOP package
for Commercial (-10° to +70° C) and Automotive grades
(-40° to +85° C). The CDB5340 Customer Demonstra-
tion Board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information”
on
page 22
for
complete
ordering
information.
The CS5340 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as set-top boxes, DVD-karaoke players, DVD record-
ers, A/V receivers, and automotive applications.
High-Pass
Filter
Low-Latency
Digital Filters
High-Pass
Filter
VA
3.3 V to 5 V
Internal
Reference
Voltages
Switch-Cap
ADC
VD
3.3 V to 5 V
VL
1.8 V to 5 V
Auto-detect
MCLK Divider
Slave Mode
Auto-detect
Master Clock
Reset
Single-Ended
Analog Input
Low-Latency
Digital Filters
Switch-Cap
ADC
Mode
Configuration
Single-Ended
Analog Input
SCLK
LRCK
SDOUT
M0
M1
FILT+
VQ
AINR
AINL
March '08
DS601F2
Confidential Draft
3/11/08
CS5340


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