CS4382-KQZ datasheet(11/42 Pages) CIRRUS

Il numero della parte	CS4382-KQZ

Spiegazioni elettronici	114 dB, 192 kHz 8-Channel D/A Converter

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Produttore elettronici	CIRRUS [Cirrus Logic]

Homepage	http://www.cirrus.com

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DS514F2

11

CS4382

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® FORMAT

(For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF)

Notes:

19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

21.

for Single-Speed Mode,

for Double-Speed Mode,

for Quad-Speed Mode.

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

-

100

kHz

RST Rising Edge to Start

tirs

500

-

ns

Bus Free Time Between Transmissions

tbuf

4.7

-

µs

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

-

µs

Clock Low time

tlow

4.7

-

µs

Clock High Time

thigh

4.0

-

µs

Setup Time for Repeated Start Condition

tsust

4.7

-

µs

SDA Hold Time from SCL Falling

(Note 19)

thdd

0-

µs

SDA Setup time to SCL Rising

tsud

250

-

ns

Rise Time of SCL and SDA

trc, trc

-1

µs

Fall Time SCL and SDA

tfc, tfc

-

300

ns

Setup Time for Stop Condition

tsusp

4.7

-

µs

Acknowledge Delay from SCL Falling

(Note 20)

tack

-

(Note 21)

ns

15

256

Fs

×

---------------------

15

128

Fs

×

---------------------

15

64

Fs

×

------------------

SDA

SCL

001100

ADDR

AD0

R/W

Start

ACK

DATA

1-8

ACK

DATA

1-8

ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Note 1

Figure 3. Control Port Timing - I²C Format

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