CS2100-CP-CZZ datasheet(1/32 Pages) CIRRUS

Il numero della parte	CS2100-CP-CZZ

Spiegazioni elettronici	Fractional-N Clock Multiplier

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Produttore elettronici	CIRRUS [Cirrus Logic]

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Preliminary Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Fractional-N Clock Multiplier

Features

Clock Multiplier / Jitter Reduction

–

Generates a Low Jitter 6 - 75 MHz Clock

from a Jittery or Intermittent 50 Hz to 30

MHz Clock Source

Highly Accurate PLL Multiplication Factor

–

Maximum Error Less Than 1 PPM in High-

Resolution Mode

I²C® / SPI™ Control Port

Configurable Auxiliary Output

Flexible Sourcing of Reference Clock

–

External Oscillator or Clock Source

–

Supports Inexpensive Local Crystal

Minimal Board Space Required

–

No External Analog Loop-filter

Components

General Description

The CS2100-CP is an extremely versatile system

clocking device that utilizes a programmable phase

lock loop. The CS2100-CP is based on a hybrid ana-

log-digital PLL architecture comprised of a unique

combination of a Delta-Sigma Fractional-N Frequency

Synthesizer and a Digital PLL. This architecture allows

for generation of a low-jitter clock relative to an exter-

nal noisy synchronization clock at frequencies as low

as 50 Hz. The CS2100-CP supports both I²C and SPI

for full software control.

The CS2100-CP is available in a 10-pin MSOP pack-

age in Commercial (-10°C to +70°C) grade. Customer

development kits are also available for device evalua-

tion. Please see “Ordering Information” on page 32 for

complete details.

I²C / SPI

Auxiliary

Output

6 to 75 MHz

PLL Output

3.3 V

I²C/SPI

Software Control

8 MHz to 75 MHz

Low-Jitter Timing

Reference

Fractional-N

Frequency Synthesizer

Digital PLL & Fractional

N Logic

Output to Input

Clock Ratio

N

Timing Reference

PLL Output

Lock Indicator

50 Hz to 30 MHz

Frequency

Reference

Frequency Reference

JUN '08

DS840PP1

CS2100-CP

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