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TEA1750T Scheda tecnica(PDF) 5 Page - NXP Semiconductors |
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TEA1750T Scheda tecnica(HTML) 5 Page - NXP Semiconductors |
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5 / 29 page  TEA1750_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 December 2008 5 of 29 NXP Semiconductors TEA1750 GreenChip III SMPS control IC 7. Functional description 7.1 General control The TEA1750 contains a controller for a power factor correction circuit as well as a controller for a flyback circuit. A typical configuration is shown in Figure 3. 7.1.1 Start-up and undervoltage lock-out Initially the capacitor on the VCC pin is charged from the high voltage mains via the HV pin. As long as VCC is below Vtrip, the charge current is low. This protects the IC in case the VCC pin is shorted to ground. For a short start-up time the charge current above Vtrip is increased until VCC reaches Vth(UVLO). If VCC is between Vth(UVLO) and Vstartup, the charge current is low again, ensuring a low duty cycle during fault conditions. The control logic activates the internal circuitry and switches off the charge current when the voltage on pin VCC passes the Vstartup level. First, the LATCH pin output is activated and the soft-start capacitors on the PFCSENSE and FBSENSE pins are charged. When the LATCH pin voltage exceeds the Ven(LATCH) voltage and the soft-start capacitor on the PFCSENSE pin is charged, the PFC circuit is activated. The supply current from the HV pin is then switched on again and the PFC circuit charges the Cbus capacitor. When the voltage on pin VOSENSE reaches the Vstart(fb) level, the charge current is switched off and the flyback converter is activated (providing the soft-start capacitor on the FBSENSE pin is charged). The output voltage of the flyback converter is then regulated to its nominal output voltage. The IC supply is taken over by the auxiliary winding of the flyback converter. See Figure 4. Fig 3. Typical configuration of TEA1750 12 11 9 16 13 8 6 7 3 2 10 4 1 TEA1750T 014aaa016 |
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