 |
Motore di ricerca datesheet componenti elettronici |
|
|
Motore di ricerca datesheet componenti elettronici |
|
ADE5169ASTZF62-RL Scheda tecnica(PDF) 9 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADE5169ASTZF62-RL Scheda tecnica(HTML) 9 Page - Analog Devices |
|
|
9 / 148 page  ADE5166/ADE5169 Rev. 0 | Page 9 of 148 TIMING SPECIFICATIONS AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1 and at 0.45 V for Logic 0. Timing measurements were made at VIH minimum for Logic 1 and at VIL maximum for Logic 0, as shown in Figure 2. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs, as shown in Figure 2. CLOAD for all outputs = 80 pF, unless otherwise noted. VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted. V – 0.5V 0.45V 0.2VSWOUT + 0.9V TEST POINTS 0.2VSWOUT – 0.1V VLOAD – 0.1V VLOAD VLOAD + 0.1V TIMING REFERENCE POINTS VLOAD – 0.1V VLOAD VLOAD – 0.1V SWOUT Figure 2. Timing Waveform Characteristics Table 5. Clock Input (External Clock Driven XTAL1) Parameter 32.768 kHz External Crystal Parameter Description Min Typ Max Unit tCK XTAL1 period 30.52 μs tCKL XTAL1 width low 6.26 μs tCKH XTAL1 width high 6.26 μs tCKR XTAL1 rise time 9 ns tCKF XTAL1 fall time 9 ns 1/tCORE Core clock frequency1 1.024 MHz 1 The ADE5166/ADE5169 internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 25). Table 6. I2C-Compatible Interface Timing Parameters (400 kHz) Parameter Description Typ Unit tBUF Bus-free time between stop condition and start condition 1.3 μs tL SCLK low pulse width 1.36 μs tH SCLK high pulse width 1.14 μs tSHD Start condition hold time 251.35 μs tDSU Data setup time 740 ns tDHD Data hold time 400 ns tRSU Setup time for repeated start 12.5 ns tPSU Stop condition setup time 400 ns tR Rise time of both SCLK and SDATA 200 ns tF Fall time of both SCLK and SDATA 300 ns tSUP1 Pulse width of spike suppressed 50 ns 1 Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of <50 ns. MSB tBUF SDATA (I/O) SCLK (I) STOP CONDITION START CONDITION REPEATED START LSB ACK MSB 1 2TO 7 89 1 S(R) PS tPSU tDSU tSHD tDHD tDSU tDHD tSUP tH tSUP tL tRSU tR tR tF tF Figure 3. I2C-Compatible Interface Timing |
Codice articolo simile - ADE5169ASTZF62-RL |
|
Descrizione simile - ADE5169ASTZF62-RL |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEETIT.COM |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Italian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
