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AD5422AREZ Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD5422AREZ Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 38 page AD5412/AD5422 Preliminary Technical Data Rev. PrF | Page 6 of 38 Parameter Value1 Unit Test Conditions/Comments Load Current 5 mA typ Short Circuit Current 7 mA typ Line Regulation2 10 ppm/V typ Load Regulation2 TBD ppm/mA Thermal Hysteresis2 TBD ppm DIGITAL INPUTS2 DVCC = 2.7 V to 5.5 V, JEDEC compliant VIH, Input High Voltage 2 V min VIL, Input Low Voltage 0.8 V max Input Current ±1 µA max Per pin Pin Capacitance 10 pF typ Per pin DIGITAL OUTPUTS 2 SDO VOL, Output Low Voltage 0.4 V max sinking 200 µA VOH, Output High Voltage DVCC − 0.5 V min sourcing 200 µA High Impedance Leakage Current ±1 µA max High Impedance Output Capacitance 5 pF typ FAULT VOL, Output Low Voltage 0.4 V max 10k Ω pull-up resistor to DV CC VOL, Output Low Voltage 0.6 V typ @ 2.5 mA VOH, Output High Voltage 3.6 V min 10k Ω pull-up resistor to DV CC POWER REQUIREMENTS AVDD 10.8 to 40 V min to V max AVSS -26.4 to 0 V min to V max |AVSS | + AVDD 10.8 to 52.8 V min to V max DVCC Input Voltage 2.7 to 5.5 V min to V max Internal supply disabled Output Voltage 4.5 V typ DVCC can be overdriven up to 5.5V Output Load Current 5 mA typ Short Circuit Current 20 mA typ AIDD TBD mA Output unloaded AISS TBD mA Output unloaded DICC 1 mA max VIH = DVCC, VIL = GND, TBD mA typ Power Dissipation TBD mW typ AVDD = 40V, AVSS = 0 V, VOUT unloaded TBD mW typ AVDD = 40V, AVSS = -15 V, VOUT unloaded TBD mW typ AVDD = 15V, AVSS = -15 V, VOUT unloaded 1 Temperature range: -40°C to +85°C; typical at +25°C. 2 Guaranteed by characterization. Not production tested. |
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