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TEA2028 Scheda tecnica(PDF) 8 Page - STMicroelectronics |
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TEA2028 Scheda tecnica(HTML) 8 Page - STMicroelectronics |
8 / 47 page - In practice, at low amplitude video signals, it is recommended to insert a low-pass filter before the ”C27” capacitor so as to attenuate the chromi- nance sub-carrier and the noise components. The aim is to reduce the phase variations of the detected sync pulse and thus enhance the hori- zontal scanning stability. 27 220nF 1k Ω CC V + Chroma Burst Figure 8 V.2.2 - Memorizing the sync pulse 50% value The objective is to memorize the voltage corre- sponding to 50% of the line sync pulse VS1 by using an external capacitor connected to Pin 26 (see Figure 9). The overall arrangement comprises two compara- tors. - Comparator C2 : delivers an output voltage ”V1” by comparing VS1 +VD,V26 and the voltage drop across two resistors. - Comparator C3 : which delivers a constant output current thereby maintaining on capacitor ”C26”, the voltage V50% corresponding to 50% of peak to peak sync pulse. During the line scanning, diode ”D” is reverse bi- ased : VS1 +VD =V1 <V26 and C3 will deliver a current ID which will discharge the capacitor. During sync pulse interval, VS1 +VD =VP +VD, diode ”D” begins conducting and thus : V1 =(VP +VD)- (2 R i1). Since the capacitor has been slightly discharged ⇒ V1 >V26, comparator C3 begins charging the capacitor until C2 is brought to equilibrium. At this time, I1 = i 2 where i = V26 − VD − VN R thus V1 =VP +VD =2 i 2 =VP +VN +2 VD -V26 and V1 =V26 ⇔ V26 = VP + VN 2 +VD =V50% A high value C26 capacitor will thus memorize the voltage level correspondingto 50% of the line sync. pulse. V.2.2.1 - IC ID Ratio calculation During the line scanning period (TH -TS), the capacitor C26 will loose a charge equivalent to : ID (TH -TS). This energy must be recovered before the end of sync pulse such that : IC ⋅ tS >ID (TH -TS) therefore IC ID > TH − tS tS IC ID > 12.6 In practice, for C26 = 100nF, ID =25 µAand IC = 800 µA. i R VN CC V + V50% IC ID V1 V + V S1 D i 1 C2 2R xK CC V + 26 C26 t V + V S1 D V50% V + V ND 0 I26 V26 IC ID t S V1 V + V P D D t t t V50% 0 0 V50% Figure 9 TEA2028 - TEA2029 APPLICATION NOTE 8/46 |
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