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TDA7552 Scheda tecnica(PDF) 6 Page - STMicroelectronics |
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TDA7552 Scheda tecnica(HTML) 6 Page - STMicroelectronics |
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6 / 12 page  24 BIT DSP CORE The DSP Core is a general purpose 24-bit DSP. The main feature of the DSP Core are listed be- low: 50Mhz Operating Frequency (50 MIPS) Single cycle multiply and accumulate 2x56-bit Accumulators Double precision multiply Convergent rounding Scaling and saturation arithmetic 48-bit or 2x24-bit parallel moves 64 interrupt vector locations Fast or long interrupts possible Programmable interrupt priorities and masking 8 each Address Registers, Address Offset Registers and Address Modulo Registers Linear, Reverse Carry, Multiple Buffer Modulo, Multiple Wrap-around Modulo address arith- metic Post-increment or decrement by 1 or by offset, Index by offset, predecrement address Repeat instruction and zero overhead DO loops Hardware stackcapable of nesting 7 DO loops or 15 interrupts/subroutines Bit manipulation instructions possible on all registers and memory locations. Also Jump on bit test. Data Arithmetic Logic Unit (DALU) Address Generation Unit (AGU) Program Control Unit (PCU) Three Data Buses Three Address Buses Internal Data Bus Switch bit Manipulation Unit Debug Logic Memories 16384x24-bit Program ROM used for storing the program code. 16384x24-bit Data RAM used for storing Data. DSP peripherals Serial Audio Interface (SAI) The SAI is used to deliver digital audio to the DSP from an external source and to deliver digital audio from the DSP to an external DAC. It allows using an external CODEC. The main features of this block are listed below: – One Data Transmission Line – One Data Reception Line – Master and Slave Operating Modes – Reference clock for transmission supplied – Transmit and Receive Interrupt Logic modified to trigger on Left/Right data pairs – Receive and Transmit Data Registers have two locations to hold left and right data I 2C interface/SPI The inter integrated-circuit bus is a simple bi- directional two-wire bus used for efficient inter IC control. All I 2C bus compatible devices in- corporate an on-chip interface which allows them communicate directly with each via the I 2C bus. Every component hoocked up to the I 2C bus has it’s own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and/or transmitter depending on it’s functional- ity. The Serial Peripheral Interface (SPI) can be enabled instead of the I 2C interface. During an SPI transfer, data is trasmitted and received simulaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slve SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. The central element in the SPI system is the shift register and the read data buffer. The sys- tem is single buffered in the trasmit direction and double buffered in the receive direction. EMI The External Memory Interface is viewed as a memory mapped peripheral. Data transfers are performed by moving data into/from data regis- ters and the control is exercised by polling status flags in the control/status register or by servicing interrupts. An external memory write is executed by writing data into the Data Write register. An external memory read operation is executed by either writing to the Offset register or reading the Data read register, depending on the configuration. The main features of the EMI are listed below: – Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM – 22 bit address bus multiplexed with an 8 bit data bus – Three choices of data word lenghths, 8, 16 or 24 bits in SRAM mode – Two choices of data word lenght, 16 or 24 bits in DRAM mode – Thirteen address lines 2 26= 256Mbits TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553 6/12 |
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