Motore di ricerca datesheet componenti elettronici |
|
TDA7330BD Scheda tecnica(PDF) 4 Page - STMicroelectronics |
|
TDA7330BD Scheda tecnica(HTML) 4 Page - STMicroelectronics |
4 / 9 page OUTPUT TIMING The generated 1187.5Hz output clock (RDCL line) is synchronized to the incoming data. According to the internal PLL lock condition this data change can results on the falling or on the rising clock edge. Whichever clock edge is used by the decoder (ris- ing or falling edge) the data will remain valid for 416.7 µsec after the clock transition. Figure 2: RDS timing diagram Figure 3: Test Circuit Measure f1 (KHz) f2 (KHz) f3 (KHz) ∆Ph max A 56.5 57 57.5 <5 ° B 56 57 58 <7.5 ° C 55.5 57 58.5 <10 ° Note(2): The 3th harmonic (57KHz) must be less than -40dB in respect to the input signal 19KHz plus gain. ELECTRICAL CHARACTERISTICS (continued) TDA7330B 4/9 |
Codice articolo simile - TDA7330BD |
|
Descrizione simile - TDA7330BD |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |