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STD12NM50N Scheda tecnica(PDF) 4 Page - STMicroelectronics |
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STD12NM50N Scheda tecnica(HTML) 4 Page - STMicroelectronics |
4 / 19 page Electrical characteristics STB12NM50N - STD12NM50N - STI/F12NM50N - STP12NM50N 4/19 2 Electrical characteristics (TCASE=25 °C unless otherwise specified) Table 5. On/off states Symbol Parameter Test conditions Min Typ. Max Unit V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS= 0 500 V dv/dt(1) 1. Characteristic value at turn off inductive load Peak diode recovery voltage slope VDD=400 V, ID=11 A, VGS=10 V 44 V/ns IDSS Zero gate voltage drain current (VGS = 0) VDS = max rating, VDS = max rating@125 °C 1 100 µA µA IGSS Gate body leakage current (VDS = 0) VGS = ±20 V 100 nA VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA 23 4 V RDS(on) Static drain-source on resistance VGS= 10 V, ID= 5.5 A 0.29 0.38 Ω Table 6. Dynamic Symbol Parameter Test conditions Min Typ. Max Unit gfs (1) 1. Pulsed: pulse duration=300 µs, duty cycle 1.5% Forward transconductance VDS =15 V, ID = 5.5 A 8S Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS =50 V, f=1 MHz, VGS=0 940 100 10 pF pF pF Coss eq (2) 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Equivalent output capacitance VGS=0, VDS =0 to 400 V 130 pF Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD=400 V, ID = 11 A VGS =10 V (see Figure 17) 30 6 15 nC nC nC Rg Gate input resistance f=1 MHz Gate DC Bias=0 test signal level=20 mV open drain 4.5 Ω |
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