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FST3244 Scheda tecnica(PDF) 6 Page - Fairchild Semiconductor |
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FST3244 Scheda tecnica(HTML) 6 Page - Fairchild Semiconductor |
6 / 9 page © 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com FST3244 • Rev. 1.0.3 6 Physical Dimensions 0.10 C C A SEE DETAIL A NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. E) LANDPATTERN STANDARD: SOIC127P1030X265-20L PIN ONE INDICATOR 0.25 1 10 B CA M 20 11 B X 45° 8° 0° SEATING PLANE GAGE PLANE DETAIL A SCALE: 2:1 SEATING PLANE LAND PATTERN RECOMMENDATION F) DRAWING FILENAME: MKT-M20BREV3 0.65 1.27 2.25 9.50 13.00 12.60 11.43 7.60 7.40 10.65 10.00 0.51 0.35 1.27 2.65 MAX 0.30 0.10 0.33 0.20 0.75 0.25 (R0.10) (R0.10) 1.27 0.40 (1.40) 0.25 D) CONFORMS TO ASME Y14.5M-1994 Figure 5. 20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300-inch Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ |
Codice articolo simile - FST3244_08 |
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Descrizione simile - FST3244_08 |
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