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FIN212AC Scheda tecnica(PDF) 6 Page - Fairchild Semiconductor

Il numero della parte FIN212AC
Spiegazioni elettronici  12-Bit Serializer Deserializer with Multiple Frequency Ranges
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN212AC Rev. 1.0.6
6
Serializer Operation Mode (DIRI=1)
The serializer configurations are described in the
following sections. The basic serialization circuitry
works similarly in all modes, but the actual data and
clock streams differ if the frequency of CKREF is the
same as or greater than the STROBE frequency. When
CKREF equals STROBE, the CKREF and STROBE
signals are physically connected together and are one
signal. When CKREF does not equal STROBE, each
signal is distinct and CKREF must be running at a
frequency high enough to avoid any loss of data
condition. CKREF must never be a lower frequency
than STROBE. For proper serialization, the PLL should
be stable and locked prior to sending valid data. For the
following modes, refer to Table 1.
MODE 1,2,3; PLL1=0, PLL0=1;
CKREF Equals STROBE
This mode is typically used when sending pixel data at
a constant rate. Data is captured on the rising edge of
the STROBE signal and serialized. The serial CLK
frequency is exactly seven times the clock frequency.
For example, a CKREF frequency of 10MHz results in a
serial CLK frequency of 70MHz and a data transfer rate
of 140Mbps. The serialized data stream is synchronized
and sent source synchronously with a bit clock.
MODE 1,2,3; PLL1=0, PLL0=1;
CKREF Does Not Equal STROBE
For microcontroller interfaces, a reference clock at the
same frequency as the strobe is typically not available.
Data transfers are typically not synchronous. To
accommodate this type of transfer, a reference clock of a
higher frequency than the fastest strobe frequency must
be provided to the CKREF signal. The CKREF clock
signal must be continuously running for as long as data is
being transferred. The actual serial transfer rate is
dependent on the CKREF and the parallel transfer rate
depends on the STROBE frequency. A data value of zero
is sent when no valid data is present in the serial bit
stream. The operation of the serializer otherwise remains
the same. The exact frequency that the reference clock
needs to run is dependent upon the stability of the
CKREF and STROBE signal. If the source of the CKREF
signal implements spread spectrum technology, the
minimum frequency of this spread spectrum clock should
be used in calculating the ratio of STROBE frequency to
the CKREF frequency. Similarly if the STROBE signal
has significant cycle-to-cycle variation, the maximum
cycle-to-cycle time needs to be factored into the selection
of the CKREF frequency. A STROBE frequency of 7MHz
and a CKREF of 11MHz results in serial CLK frequency
seven times the CKREF (77MHz) and a data transfer rate
of 154Mbps.
MODES (1,2,3); PLL1=1,PLL0=0 (Divide-by-2) or
PLL1=1,PLL0=1 (Divide-by-3)
For some microcontroller applications, the available
reference frequency is significantly faster than the
STROBE frequency required for the application. To
more closely match the serial frequency with the strobe,
the reference frequency can be divided by two or three.
The serializer works identically to when CKREF is not
equal to STROBE. Refer to the Deserializer Operation
Mode section below for details.
Deserializer Operation Mode
The operation of the deserializer is dependent upon the
data received on the DSI data signal pair and the CKSI
clock signal pair. The following sections describe the
operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and
STROBE signals refer to the signals associated with the
serializer device used to generate the serial data and
clock signals. When operating in this mode, the internal
serializer circuitry is disabled, including the parallel data
input buffers. If there is a CKREF signal provided, the
CKSO serial clock continues to transmit bit clocks.
DIRI = 0; Serializer Source: CKREF Equals STROBE
When the DIRI signal is asserted LOW, the device is
configured as a deserializer. Data is captured on the
serial port and deserialized through a bit clock sent with
the data. The falling edge of CKP occurs coincident with
the parallel data transition.
DIRI=0
; Serializer Source:
CKREF Does Not Equal STROBE
The logical operation of the deserializer remains the
same whether CKREF is equal in frequency to STROBE
or at a higher frequency than STROBE. The duty cycle
of CKP varies based on the ratio of the frequency of the
CKREF signal to the STROBE signal. The average
frequency of the CKP signal is equal to the STROBE
frequency. The falling edge of CKP is coincident with
data transition. The LOW time of the CKP signal is set
by the state of the PWS1 and PWS0 signals.


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